As semiconductor technology progresses, designers continue to find ways to assemble multiple integrated circuits (ICs) into denser arrangements. One such arrangement disclosed in U.S. patent application Ser. No. 12/136,868, filed Jun. 11, 2008, is shown in FIG. 1, with which familiarity is assumed. Illustrated there is a memory system 100 mounted to a printed circuit board (PCB) 30. The system 100 includes a standard memory controller 12. Memory controllers 12 are well known in the art and work to create a standard interface with which a microprocessor or other memory querying system (not shown) can predictably communicate. Memory controller 12 typically comprises an integrated circuit separate and independent from other components in the system 100, but this is not strictly necessary, and the controller 12 could be integrated with other components if desired. The memory controller is affixed to the PCB 30 using solder bumps 80, as is typical.
Also present in system 100 is a multi-IC system 40. The multi-IC system 40 integrates a logic IC 14 and a set 25 of modified Random Access Memory (RAM) ICs 16x into a single package. As discussed in the above-mentioned '868 application, the logic IC 14 can contain logic circuits traditionally present on memory integrated circuits, as well as other circuits relevant to integration. As a result of these logic circuits being moved onto the logic IC 14, the modified RAM ICs 16x need not contain such circuits, and can therefore be made smaller. The multi-IC system 40 is also affixed to the PCB 30 using solder bumps 82.
As shown, the logic IC 14 and the modified RAM ICs 16x are vertically stacked in the multi-IC system 40 within a singular package. (“Vertical” in this context should be understood as being generally perpendicular to the major plane of an IC). To facilitate the running of the signals between the various ICs in the multi-IC system, interconnects, such as Through Wafer Interconnects (TWIs) 83, run though the logic IC 14 and the modified RAM ICs 16x. As is well known, the TWIs 83 comprise a conductive plug of material set in a hole that has been milled, drilled, or etched at least partially through the substrate 85 of each of the ICs. For example, the tops and bottoms of the TWIs 83 can be made to communicate with TWIs on adjacent ICs in the stack via solder bumps 84, in effect creating a bus 15 within the multi-IC system 40 common to at least some of the ICs in the system (e.g., the modified RAM ICs 16x). Each set 41 of TWIs 83 thus passes a signal vertically through the multi-IC system 40.
FIG. 2 shows multi-IC system 40 in a schematic form. Bus 15 is apparent, which as mentioned above is formed from the various TWIs 83 in the logic IC 14 and the modified RAM ICs 16x, and from solder bumps 84 that connect them. As drawn, it is assumed that there are ‘n’ signals in the bus 15, and ‘i’ modified RAM ICs 16x. As is typical, each IC contains transmitter (T) and receiver (R) circuitry for driving and sensing data on the bus 15. Thus, T(x,y) represents the transmission circuitry used to send data from the xth modified RAM IC 16 onto the yth of the traces in bus 15; likewise, R(x,y) represents the transmission circuitry used to sense data at the xth modified RAM IC 16 from the yth of the traces in bus 15. T(L,y) and R(L,y) respectively represent the transmission and receiver circuitry for the logic IC 14.
As one skilled in the art will realize, which of the transmission or reception circuitry is enabled at any given time on a given IC depends on the particular action that is occurring within the multi-IC system 40. For example, if data is being written in parallel from the logic IC 14 to the second modified RAM IC 162 along bus traces 1 though 8, then T(L,1) through T(L, 8) would be activated on the logic IC 14 along with R(2,1) through R(2,8) on the modified RAM IC 162. If data transfer occurs in the other direction, i.e., if data is read from modified RAM IC 162, then R(L,1) through R(L,8) would be activated on the logic IC 14 along with T(2,1) through T(2,8) on the modified RAM IC 162. Some of the traces may not allow for two-way transmission. For example, bus trace n-1 as illustrated can only pass data from the logic IC 14 to the RAM ICs 16x, perhaps because such a trace merely contains a control signal for the RAM ICs.
Vertical integration makes multi-IC system 40 physically more compact, such that it takes up less area on PCB 30 than would its individual ICs (14; 161 through 16i) if arrayed on the PCB 30. Equally important, vertical integration minimizes the distance signals must travel between the ICs, i.e., it shortens the lengths of the traces that comprise bus 15. Shorter traces theoretically allow signals to travel more quickly on the bus 15. More importantly, shorter traces may reduce transmission line effects (e.g., signal reflections) and the capacitive loading seen by the transmitter, the latter of which either allows for an increased number of destinations, or lower power for a given number of destinations. Quicker signal transmission is of great benefit in modem-day systems 100 in which designers desire to send signals at ever-increasing speeds.